Low Power Design and Optimization- Spring, 2007

VADA (VLSI Algorithmic Design Automation) Lab.
Department of Electrical and
Computer Engineering Sungkyunkwan University


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To foster design innovation and creative thinking, a major part ofthe class grade is based on a design project. The idea of the project is to study one of the current "hot items" in DSP design and to propose, analyze and design a novel solution to one of those problems.The project is performed in person or groups of two and will span the complete semester. The course is graded on the basis of a final project. Given the link to present research activities we expect a number of projects will eventually be published in Conference Proceedings.

Schedule

WEEK 1-5: Literature Study (> 4 papers) - Formulation of Design Project

WEEK 6(March 29): Proposal of Topic (Style and Guide)

WEEK 7-10: Design Execution.

WEEK 11 (April 26): Posting of interim result report (Style and Guide)

WEEK 12-15: Design Execution.

WEEK 16(June 14): Presentation of Design Results (Style and Guide)

Topics

As the recurring themes of the class are low power and timing, it is encouraged to select the design projectin one of those topics. Especially recommended are projects that are relatedto Lower Power Design, as this is the special team of this semesters class. Other interesting topics are welcome as well. To give some initial guidance, a list of potential topic areas is given below.

  • Lower Power Modular Multiplier (ref. A. Bernal and A. Guyot, Hardware for computing Modular Multiplcation Algorithm, TIMA Lab. Grenoble, France)
  • Low Power Circuit using Adiabatic Computing
  • Low Power Wave Pipelined Design
  • Low Power Self-timed Design
  • Low Power Logic/Layout Design
  • High Speed, Low Power Digital Error Correction Architectures for A/D


Converters

  • Lower Power Convolutional Decoder
  • Lower Power Wireless Communication
  • Lower Power signal processing/Multimedia Processor
  • Floorplanning, Placement and Synthesis for Performance (dealing with problems due to long wire delays in sub-micron CMOS)
  • DSP Instruction Set and Architectural Features (study Pine/Oak, TI chips)
  • Trading off Speed and Power in deep Sub-Micron CMOS Clocking systems
  • Modulation Schemes in VLSI for Wireless
  • Wave-pipelining Analysis and Design
  • Memory Systems of the Future (as more and more memory fits on-chip, how should memory hierarchies be organized)
  • Power Budgetting in VLSI for Wireless Communications
  • Advanced MPEG architectures and chips
  • ATM hardware
  • Reed-Solomon chips
  • Encryption Chips
  • Your own hot topic, whacky ideas ...

More on Hot Topics

Low power Designs
Multimidea Designs
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