Low Power Design and Optimization- Spring, 2007

VADA (VLSI Algorithmic Design Automation) Lab.
Department of Electrical and
Computer Engineering Sungkyunkwan University


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Reading & Background Material

Selected readings from the following books

W.J. Dally and J.W. Poulton, "Digital System Engineering", Cambridge UniversityPress, 1998.

A. Chandrakasan and R. Brodersen, "Low-Power CMOS Design", IEEE Press,1998.

M. Elmasry, ed. "Digital MOS Integrated Circuits II", IEEE Press, 1992.

S. Tewksbury, Microelectronic System Interconnections: Performance andModeling" , IEEE Press, 1994.

J. Rabaey and M. Pedram, ed., "LowPower Design Methodologies" , Kluwer Academic Publishers, 1996.

A. Chandrakasan and R. Brodersen, "LowPower Digital CMOS Design", Kluwer Academic Publishers, 1995.

Computer Technology and Architecture: An Evolving Interaction" Hennessy and Jouppi, Computer, September 1991.

Gigabit Age Microelectronics and Their Manufacture", Chatterjee and Larrabee, IEEE Trans on VLSI, March 1993.

Circuit and Architecture Trade-offs for High-Speed Multiplication", Song and Demicheli, {\em Jou. Solid-State Circ.}, September 1991.

Pipelining Communications in Large VLSI/ULSI Systems", Audet et al, {\em IEEE Trans on VLSI}, March 1994.

Performance of Synchronous and Asynchronous Schemes for VLSI Systems", Afgahi and Svensson {\em IEEE Trans on Computers}, July 1992.

Architecture of the Pentium Microprocessor", Alpert and Avnon {\em IEEE Micro}, June 1993.

``PowerPC 601 and Alpha 21064: A Tale of Two RISCs", Smith and Weiss {\em Computer}, June 1994.

``PowerPC 604 RISC Microprocessor", Song, Denman and Chang {\em IEEE Micro}, October 1994.

Disk System Architectures for High Performance Computing", Katz, Gibson, Patterson {\em IEEE Proceedings}, December 1989.

``New Alternatives in High-Bandwidth Interfaces", B. Garrett, {\em ASIC and EDA}, August 1993.

``Computer Architecture for Digital Signal Processing", J. Allen, {\em IEEE Proceedings}, May, 1985.

``Designing the TFP Microprocessor", P. Hsu, {\em IEEE Micro}, April 1994.

``Hardware Requirements for Neural Network Pattern Classifiers", B. Boser et al {\em IEEE Micro}, February 1992.

``An Associative Processing Module for a Heterogeneous Vision Architecture", Storer et al {\em IEEE Micro}, June 1992.

``A Shared Memory MPP from Cray Research", Koeninger et al, {\em Digital Technical Journal}, Spring 1994.

``Building and Using a Highly Parallel Programmable Logic Array", Gokhale et al, {\em Computer}, January 1991.

``The Spring Scheduling Co-processor: Design, Use and Performance", Niehaus et al, {\em Proc. of Real-time Systems Symposium}, 1993.
VLSI Architectures for High-Performance Computing, Wayne Burleson at UMASS

Class-Related Links

  1. TI C54x Processor
  2. TI C6x Processor
  3. DSP Canvas
  4. Shareware CAD/CAE software
  5. Intel MMX Homepage
  6. Commercial VLSI CAD information
  7. Motorola DSP site
  8. Lower Power DSP Slides

comments and suggestions

updated on Feb. 25, 1999