Digital Logic

VADA (VLSI Algorithmic Design Automation) Lab.
Department of Electrical
Engineering Sungkyunkwan University



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Lecturer: Prof. Jun-Dong Cho Email: jdcho@skku.ac.kr , Room 21203A, Office:031-290-7127, H.P:018-332-7127

Office hours: After class or by appointments.

TA:  Seung Hoon Lee,  Room 21119 (tel: 7127)

Prerequisite: Some interests in Digital system design using VHDL is preferrable.

Homework: Notes and Homeworks are available in the web page and due in class.

Grading:

A . Project-oriented model: 10% project proposal+ 20% final project report (no late project) + 60% final exam(Solution) + 10% H.W (including the number of class absences)

or

B . Exam-oriented model: 90% final exam(Solution) + 10% H.W (including the number of class absences)

Course description

This course aims to convey a knowledge of basic concepts of logic design and design automation for digital LSI and VLSI components. Boolean algebra, combinatorial circuits including arithmetic circuits and regular structures, sequential circuits including finite-state-machines, use of programmable logic devices. Simulation and high-level specification techniques are emphasized. Emphasis is also on the logic design, optimization of either very high speed, high density or low power logic circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery.
This semester, special attention will be given to the following topics: digital logics for high-speed, low cost and lower power. This will reflected in both the lectures and the preferred projects.

Digital Logic Design Experiments: Design Practices

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