VLSI Design for Digital Signal Processing - Spring, 2000

VADA (VLSI Algorithmic Design Automation) Lab.
Department of Electrical and Computer Engineering Sungkyunkwan University

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To foster design innovation and creative thinking, a major part ofthe class grade is based on a design project. The idea of the project is to study one of the current "hot items" in DSP design and to propose, analyze and design a novel solution to one of those problems.The project is performed in person. The course is graded on the basis of a final project and seminar presentation. Given the link to present research activities we expect a number of projects will eventually be published in Conference Proceedings.

Schedule

  • WEEK 1-5: Literature Study (> 4 papers) - Formulation of Design Project
  • WEEK 6: Proposal of Topic (Style and Guide)
  • WEEK 7-10: Design Execution.
  • WEEK 11 (April 26): Presentation of interim result and submit a interim report (Style and Guide)
  • WEEK 12-15: Design Execution.
  • WEEK 16(June 7): Presentation of Design Results (Style and Guide) and submission of the research paper (double column, 4 pages).
  • Topics

    As the recurring themes of the class are low power, it is encouraged to select the design projectin one of those topics. Especially recommended are projects that are relatedto Lower Power Design in System on Chip and Embedded system applications. Interesting topics are welcome as well. To give some initial guidance, a list of potential topic areas is given below.
    • Low Power Bus Architecture for System on A Chip Design
    • Low Power Software Defined Radio
    • Low Power Embedded System Architecture
    • Lower Power Modular Multiplier (ref. A. Bernal and A. Guyot, Hardware for computing Modular Multiplcation Algorithm, TIMA Lab. Grenoble, France), Encryption Chips
    • Low Power Circuit using Adiabatic Computing
    • Low Power Wave Pipelined Design
    • Low Power Self-timed Design
    • Lower Power Convolutional Decoder, Reed-Solomon chips
    • Floorplanning, Placement and Synthesis for Performance (dealing with problems due to long wire delays in sub-micron CMOS)
    • DSP Instruction Set and Architectural Features (study Pine/Oak, TI chips)
    • Trading off Speed and Power in deep Sub-Micron CMOS Clocking systems
    • Modulation Schemes in VLSI for Wireless
    • Memory Systems of the Future (as more and more memory fits on-chip, how should memory hierarchies be organized)
    • Power Budgetting in VLSI for Wireless Communications
    • Advanced MPEG architectures and chips
    • ATM hardware
    • Your own hot topic, whacky ideas ...

    More on Hot Topics

    Low power Designs
    Multimidea Designs
    Other CAD issues

    Reports


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    Project Proposal and Report Web Board