Computer Aided Design of Digital Integrated Circuits; Spring, 2002

VADA (VLSI Algorithmic Design Automation) Lab.
Department of Electrical and Computer Engineering Sungkyunkwan University

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To foster design innovation and creative thinking, a major part ofthe class grade is based on a design project. The idea of the project isto study one of the current "hot items" in digital circuit design and to propose, analyze and design a novel solution to one of those problems.The project is performed in groups of two and will span the complete semester.


  • WEEK 1-5: Literature Study (> 4 papers) - Formulation of Design Project
  • WEEK 8(April 14): Presentation of Topic Proposal (5 minutes) (Style and Guide)
  • WEEK 9-13: Design Execution.
  • WEEK 13 (May 19): Posting of interim result report (Style and Guide)
  • WEEK 14-15: Design Execution.
  • WEEK 16(June 16): Presentation of Design Results (20 minutes) (Style and Guide)



    To make the results available to the complete group and to make your results more dynamic, you will be required to provided them as web-entries.


    As the recurring themes of the class are deep submicron design, signalintegrity,low power and timing, it is encouraged to select the design projectin one of those topics. Especially recommended are projects that are relatedto Lower Power Design, as this is the special team of this semesters class. Other interesting topics are welcome as well. To give some initial guidance, a list of potential topic areas is given below.

    Lower Power Circuit Designs

    • Adiabatic Computing
    • True Single-Phase Energy-Recovering Logic for Low-Power, High-Speed VLSI, (ref. Suwhan Kim and M. C. Papaefthyniou, U. of Michigan)
    • Wave Pipelining
    • Low Voltage Circuits
    • Mixing Synchronous and Self-Timed Design

    Lower Power Logic Designs

    • 32-bit Fast Multiplier VHDL code for fast multiplier
    • Local Transformation Techniques for Multi-Level Logic Circuts utilizing Circuit Symmetries for power reduction (ref. Ki-Seok Chung and C.L.Liu, UNiv. of Illinois)
    • Low Power Logic Synthesis under a General Delay model (ref. Unni Narayanan, C.L.Liu, U. of Illinois)
    • Power-Delay Tradeoffs for Radix-4 and Radix-8 Multiplier/Divider
    • Efficient Clock Gating (ref. "Dynamic Power Management", Luca Benini and G. De Micheli)
    • Clock Skew - Clock Distribution Techniques

    Lower Power Designs for Application Specific Processors

    • Decorrelating (DECOR) Transformations for Low-Power Adaptive Filters (ref. Sumant Ramprasad, Naresh R. Shandhag, and I. Hajj, U. Illinois)
    • The Logarithmic Number Systems for strength reduction in adaptive Filtering (ref. John R. Sacha and Mary. J. Irwin, Penn State Univ)
    • Low-power Vitervi decoder (ref. Source/Tutotial on Viterbi Decoder ASIC design )
    • Low-power architecture for a SOVA turbo decoder (ref. D. Garrett and Mircea Stan, Univ. of Virginia)
    • Low Power Methodology and Design techniques for processoe design (ref. J. Patrick Brennan, et al. IBM Microelectronics Division, Essex Junction, VT)
    • Power Consumption of Spread Spectrum Correlator Architectures (ref. Won Namgong and Teresa Meng, Stanford Univ.)
    • Design Methodologies for Low power signal processing (ref. Keshab. K. Parhi, Uni. of Minnesota, MN, Francky Catthoor, IMEC, Leuven, Belgium)
    • Lower power Wireless communications (ref. Michiel Steyaert, ESAT, Leuven, Belgium and Charles Chien, Rockwell Science Centre)

    More on Hot Topics

  • Your own hot topic, whacky ideas ...
  • Some of basic project examples are here ... Examples
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