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for Electronic System Design |
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for Electronic System Design |
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| TARDIS | Monitoring of projects, information capturing, dissemination of results. |
| LOVO | Power electronics; low output voltage dc/dc converters for low power applications. |
| PAPRICA | New algorithm/architecture for RF part of DECT/GSM, compatible with digital ATMEL process (analogue processing). |
| SUPREGE | Micropower transceiver architecture for short distance wireless commu-nication (super-regenerative principle); applied to 3 demonstrators. |
| SALOMON | Techniques and tools to estimate power dissipation of high levelanalogue and digital blocks; applied to telecom examples. |
| COOL-LOGOS | Power reduction through use of local "don't care" conditions and global state resizing; applied to a high performance 24-bit DSP. |
| PCBIT | Use of power management schemes, gate level "pre-computation";low power ISDN interface for portable PCs. |
| SOFLOPO | Software (compiler) optimisation for low power (for ARM and a DSP processor); estimate power consumption of program execution. |
| PREST | Use of asynchronous design, efficient architecture and gate level design, to reduce power in a CMOS GSM chip set. |
| LPGD | Power optimisations at algorithmic and architectural level; top down design flow; integrated GFSK/GMSK modem design. |
| DESCALE | Asynchronous design ("handshake methodology") to reduce power and peak current, applied to smart card IC design. |
| AMIED | Algorithm evaluation and architecture trade-offs; asynchronous design; design flow; encryption/decryption chip design. |
| DAB-LP | Specification transformations to minimise access to large memories and distant data in DSP systems; applied to a DAB IC. |
| COLOPODS | Low power/low voltage re-design of hearing aid DSP; architecture choice; pipelining; gated clock design, routing strategy. |
| I-MODE | Design of analogue baseband filters and AD converters, based on current-mode principle; DECT/DCS1800 transceiver design. |
| ALPINS | New architecture for design of low voltage log domain filters applied to DECT and GSM handset design. |
| SB-USB | Development of software based low speed USB (universal serial bus) device around CSEM's processor core. |
| CRAFT | Design methodology for RF components for GSM/DECT; based on MOS transistor model for deep submicron and RF mode operation. |
| MELOPAS | System simulation for analyses of power consumption of mixed mode ASICs; applied to a RISC processor. |
| COSAFE | Development of an ASIC for safety critical applications, applied to infusion pump controller design. |
| LUCS | Design of digital front-end for medical diagnostic ultrasound equipment. |
EP
25213 TARDIS
Summary
The Design Clusters action aims to foster excellence in design skills, and to bring these skills to broad industrial use. Design Clusters are co-ordinated sets of design experiments comprising research and best practice work.
Cluster themes currently addressed are Low Power Design and Mixed Signal Design, co-ordinated by DIMES and CNM respectively. The specific goals are:
Objectives
Technical University of DELFT/ DIMES (NL), CNM (E), participants of all Design Experiments
Contact Point Duration
Dr. Rene van Leuken, 42 months from 16.07.97
DIMES Design and Test Centre H16 CAS
Mekelweg 4, NL-2628 CD Delft, The Netherlands
Tel: +31 15 278 66 96
Fax: +31 15 278 75 64
Cluster Homepage: http://www.esdlpd.dimes.tudelft.nl/
EP
25242 PREST
Summary
In this programme the partners will study, develop and demonstrate techniques for Low Power / Low voltage IC operation with the aim of reducing typical system power demand by a factor of ten through the application of new circuit design techniques and supply voltage reduction on an advanced bulk CMOS process.
The work will concentrate on the digital circuits identified as the main areas of current consumption in GSM personal communications integrated circuits (specifically the GPS GEM series chip-set) with the aim of raising the mobile phone performance to 1000 hours standby and 10 hours talk time between re-charging. Current systems are achieving around 100 hours standby and 2 to 4 hours talk time depending on the distance from the base station.
Objectives
GEC Plessey Semiconductors (UK), University Of Manchester (UK), Queens University, Belfast (UK) & University Of Sheffield (UK).
Contact Point Duration
Denzil Broadhurst, 24 months from 01.11.97
GEC Plessey Semiconductors
MicroElectronics Centre
Hollinwood, Oldham
OL9 7LA U.K.
Tel: +44 161 684 4025
Fax: +44 161 688 7898
E-mail: denzil.broadhurst@gpsemi.com
EP
25248 LOVO
Summary
This Design Experiment addresses new design methodologies that will contribute to a significant decrease of power dissipation in electronic equipment by decreasing the power consumption and dissipation of the DC/DC converters feeding low power electronics.
New low power systems mainly require low supply voltage. However, the lower the output voltage the lower the efficiency of the DC/DC converter. This is a very important drawback because size of the power converter is highly dependent on the efficiency, and furthermore, the ratio volume/watt in DC/DC converters is higher and higher as the output voltage is reduced. Therefore, it could be the case that future low power integrated circuits could be really small, and on the contrary the converter that feeds it would be a bulky and inefficient one.
The experiment consists of checking the feasibility of new approaches to design and manufacture DC/DC converters generating very low output voltages (< 3.3 V), required for such applications. The main features are:
Alcatel (E), Universidad Politécnica de Madrid (E)
Contact Point Duration
Enrique de la Cruz 15 months from 01.07.97
Alcatel España S.A.
Ramirez de Prado 5, 28045 Madrid, Spain
Tel: +34 1 330 4693
Fax: +34 1 330 5060
EP
25249 AMIED
Summary
The aim of the project is the development of a low-power encryption/decryption circuit for data transmission systems. The portability of these systems requires a drastic decrease of their power consumption. The International Data Encryption Algorithm (IDEA) was selected, which is one of the most powerful algorithms today.
A fully asynchronous ASIC implementation of the IDEA algorithm will be developed, which is expected to operate at frequencies up to at least 25 Mbits/sec.
An advanced low-power design flow will be established on the basis of commercially available CAD tools, which can be used also for similar data processing applications. The main effort will be spent on the algorithmic and architectural design levels, with emphasis on asynchronous design methodology.
The reduced power consumption of the asynchronous implementation will be demonstrated by comparison with a synchronous version. It will be tested in two products with different bit rate requirements. Hellenic Aerospace Industries will use the circuits in new versions of their mobile communication products.
The asynchronous design methodology and techniques will be made available to other European companies.
Objectives
Hellenic Aerospace Industry (GR), University of Patras (GR)
Contact Point Duration
Dr. Vasileios TZERMPINOS 24 months from 1.12.1997
Hellenic Aerospace Industries
R&D Division
P.O. Box 23
GR-320 09 TANAGRA
Tel. +30-262-52 537
Fax +30-262-52 170
Homepage:http://www.vlsi.ee.upatras.gr/Projects/Amient/amient.html
EP
25256 LPGD
Summary
A top-down design methodology/flow is proposed for power reduction, emphasising on optimisations at the algorithmic and architectural levels with respect to area, time and power.
The design flow includes global and local power optimisation techniques and transformations at each design level. At the algorithm level, alternatives are explored in respect of locality, complexity, parallelism, and loop transformations. At the architecture level, the switching activity problem of modules and their interconnections is reduced by techniques like power-down, memory management, clock distribution, and data representation in relation to the statistical features of input signals. At the logic level, further power optimisation may be achieved by reducing the switching activity of the nodes of a logic circuit, by technology mapping, or by multilevel logic transformations.
The design flow will be described in a universal way, so that its integration and application to other Design Environments is possible. It will be demonstrated at the example of a GFSK/GMSK MODEM, one of the most critical blocks in the entire baseband signal processing of a multi-mode DCS1800-GSM/DECT terminal.
Objectives
INTRACOM (GR); University of Patras (GR)
Contact Point Duration
INTRACOM S.A. 24 months from 01.11.97
Spyridon BLIONAS or Haralabos Karathanasis
GR-190 02 PEANIA GREECE
P.O. BOX 68
TEL.: (+30-1) 686 0442 or 686 0407
FAX: (30-1) 686 0312
E-mail: sbli@intranet.gr or bkar@intranet.gr
EP
25279 COOL-LOGOS
Summary
The partners in this project have jointly developed a high-performance 24-bit DSP which is suitable for a multitude of applications, such as decoding the AC-3 Dolby standard for digital TV audio, voice compression, multi-channel echo-cancellation, digital beam forming, etc. This DSP has been fabricated and has been demonstrated in an AC-3 decoder application.
The project partners have also been working on the development of low power design techniques aimed at achieving 25% power reduction over designs performed with our current cell-based IC design flow. These techniques are based on the exploitation of local don?t care conditions in multi-level logic circuits and gate resizing to achieve a net reduction in overall circuit power dissipation. A greedy algorithm for low power circuit node optimization using local don?t care conditions has been developed and tested in a simulation environment with encouraging results.
Objectives
DCT-Hellas (Gr), Atmel/ES2 (F)
Contact Point Duration
Stelios Koutroubinas 16 months from 01.11.96
DCT Hellas
P.O.Box 5115
26004 Patra, Greece
Tel: +30 61 453588
Fax: +30 61 453304
ESD
25400 SUPREGE
Summary
The objective is to investigate a new micropower wireless data transmission solution over short distance, in the UHF ISM frequency bands (430 and 920 MHz). The micropower transceiver will make use of an original architecture based on the super-regeneration principle. This circuit will be developed by the Electronics Laboratory of EPFL as a monolithic IC. The principle of super-regeneration, which is based on the variation of the start-up time of an oscillator as a function of the signal coupled from the antenna, allows a very simple transceiver architecture, and appears to be particularly suited to micropower applications, compared to classical solutions such as the superheterodyne, the low IF (Intermediate Frequency) or the direct conversion receiver.
The present project seeks to take up the basic idea of superregeneration by introducing original analog integrated circuits techniques for low-power performance such as automatic power-down techniques, as well as improved selectivity, sensitivity and cancellation of parasitic radiation compared to a discrete-components solution. The core of the superregeneration system being an oscillator, the receiver and transmitter functions make full use of the same circuit blocks. The whole concept has been validated by simulation. A first version of the core of the receiver has been realised in AMS BICMOS 0.8 µm technology.
The superregenerative transceiver will be used in 3 industrial applications which share the constraint of requiring micropower wireless data transmission over short distance: (1) a remote control for vehicle alarms (Transval), (2) wireless computer peripherals (Logitech), and (3) a wireless data transmission system for water counters (Mead Microelectronics).
Objectives
EPFL- LEG (CH), Transval SA (F), Logitech SA (CH), Mead sa (CH)
Contact Point Duration
Dr. Catherine DEHOLLAIN 24 months from 01.12.97
EPFL, LEG, ELB Ecublens,
CH-1015 Lausanne, Switzerland
Tel: +41 21 693 69 71
Fax: +41 21 693 36 40
Homepage:dewww.epfl.ch/leg/search_ht/search.htm
E-mail: catherine.dehollain@epfl.ch
ESD-LPD
25403 SOFLOPO
Summary
SOFLOPO will develop techniques and guidelines for mapping a specific algorithm code onto appropriate instruction subsets, so that it allows an optimal low-power code execution, for microprocessor architectures used in embedded applications. The power consumption of the code will be evaluated by means of physical measurements, instead of a detailed bottom-up simulation approach, which is unavailable due to the lack of detailed processor models. Upon these measurements, detailed models that relate software code and power dissipation will be established. These models will form the basis of developing code optimization techniques for the purpose of low-energy software execution. Extensions of existing algorithms for Interpreter optimization, that will aim at energy minimization will be developed.
This systematic modeling of the relationship between power dissipation and software code will take place for the ARM-RISC processor. An extension of the above methodologies to include DSP processors will follow. These processors constitute a big portion of embedded microprocessors. Except from specific conclusions for each architecture under inspection, general conclusions, applicable to other architectures, within some accuracy limit, will be extracted.
The viability of the derived techniques will be demonstrated by their application upon the implementation by DCT- Hellas of the IEEE 802.11 protocol microcode, used in Wireless Local Area Networks.
For their full dissemination, the results of the SOFLOPO project will be integrated into software for the power-conscious ARM-RISC and DSP code optimization. This software will be available to interested third parties. It will be also available for free to Universities under a non-disclosure agreement.
Objectives
University of Patras (GR), Data Communications Technologies-Hellas (GR)
Contact Point Duration
Dr. Thanos Stouraitis, 24 months from 01.11.97
Department of Electrical and Computer Engineering
University of Patras, Rio, 26500, GREECE
Tel: +30 61 997322
Fax: +30 61 994798
EP
25475 COLOPODS
Summary
The proposed project reduces the power consumption of the external processor of the LAURA Cochlear Implant system.
The Laura Cochlear Implant is an implantable device for the deaf and profoundly hearing impaired that electrically stimulates the auditory nerve fibres. The operation of the internal part of the LAURA cochlear implant system is controlled by an external speech processing system the size of a normal hearing aid. In this speech processor the sound signal is processed into stimulation commands that are transmitted to the internal part.
A low power implementation will make operation from standard hearing aid battery cells possible. This will mean a fundamental upgrading of the LAURA cochlear implant system and will allow a stronger position for Antwerp Bionic Systems on the world market.
It is expected that the redesign of the cochlear hearing aid Digital Signal Processor in a low power technology will reduce the processor's power consumption by a factor of 10. Through gained know-how and experience in low power optimisation, low power DSP design techniques the speech processing can be further optimised using dedicated processing architectures.
ABS has two alternatives for the low power I.C. technology for the actual implementation: a low power, high speed IMEC pilot process and a mainstream PHILIPS process that would be operated at a low voltage yielding a low power, low speed technology. Since both technologies have their own drawbacks and advantages, a pre-study is incorporated in the project to select the most appropriate technology.
Objectives
ABS (B)
Contact Point Duration
Ir Jan Janssen, 16 months from 01.12.97
Antwerp Bionic Systems N.V.
Drie Eikenstraat 661, 2650 Edegem (Belgium)
Tel: +32 3 825 26 16,
Fax: +32 2 825 06 30
EP
25476 PAPRICA
Summary
The PAPRICA project will demonstrate the capability of CMOS technology in the low power RF domain, to achieve a considerable power reduction in wireless terminals.
The main goal is to design a new architecture for RF digital mobile communication systems. The novel receiver architecture, called DOUBLE Quasi-IF with early A/D conversion (DQIF), offers a high degree of flexibility, allowing its implementation for a different number of standards, like DECT, PMR (TETRAPOL), and GSM. Since a relevant part of signal processing is performed at baseband instead of high frequency, the architecture offers a reduction in power consumption when compared with other traditional techniques, like the super-heterodyne one. Particular features are i) triple RF to baseband down-conversion, with ii) first down conversion at 150 MHz through a LO at fixed frequency, iii) second conversion of a sub-band of 3 MHz containing the desired channel, iv) third completely digital conversion after delta-sigma band-pass A/D conversion, v) final channel selection performed in the digital domain.
Due to the particular conversion technique, the electrical specifications of the most critical blocks will be less demanding, and consequently expected power consumption will be very competitive.
Project Objectives
ATMEL ES2 (F), IST (P), Matra Communication (F)
Contact Point Duration
Ben Altieri 30 months from 1 August 1997
Atmel ES2
(France)
Tel: +33.442536194
Fax: +33.442536001
EP
25485 ALPINS
Summary
The ongoing trend towards reduced supply voltages of mobile and cordless systems is mainly driven by the need to implement their digital part in modern sub-micron technologies, but it introduces serious problems for the design and verification of analogue circuits. It is the strategy of this project to reduce the minimum required supply voltage of a typical analogue signal processing circuit by focusing on the design methodology of its most critical blocks.
In this way, the well-established gm-C filter technique will be optimised for low-voltage operation, new A/D- and D/A- converter concepts will be investigated and the recently developed log-domain filter technique will be brought to commercial use. This filter principle is especially well suited for low-voltage low-power applications, since it represents internal signals by instantaneously compressed voltages, while maintaining an over-all linear transfer function.
Innovative and aggressively optimised circuits require also a more profound way of design verification. Therefore, a recently developed Formal Verification Tool will be implemented in the design environment and used for checking the new designs.
For ensuring a timely return of investment, a DECT and a GSM handset were chosen as demonstrators for this project.
Objectives
SIEMENS AG (D), SIEMENS EZM (A), Univ. Hannover (D), EPFL (CH)
Contact Point Duration
Dr. Rudolph Koch 24 months from 16.11.97
Siemens Semiconductor Group
HL SP E MS
D-81541 Munich, Germany
Tel: +49 89 636 24048
Fax: +49 89 636 23649
Homepage:www.scn.de
E-mail:
rjkoch@scn.de
EP
25518 DABLP
Summary
A channel demodulator and decoder IC for Digital Audio Broadcast (DAB), called DABchic, has been designed by Philips. This IC has a great relevance for near future markets in the digital automotive and handheld DAB terminal segment. IMEC has developed a unique low power system exploration methodology (ATOMIUM), that concentrates on algorithm and architecture transformations at a high abstraction level, and which will be applied to this application. The result will be an alternative architecture, which will be analysed by comparing the power consumption of the new design with the existing one. The power dissipation should be reduced by at least a factor of three. The direct result will be a low-power architecture to be used later in the next generation DAB channel decoder IC, marketed by Philips Semiconductors. The analysis of the result will lead to a further improvement of the ATOMIUM methodology and the supporting system exploration tools. That methodology will be used in the future for IC-architecture designs. In this consortium IMEC delivers the methodology so it becomes available for the Philips design centres. IMEC on the other hand improves the methodology by using the industrial experience.
Objectives
An existing state of the art system-level low-power IC design methodology, ATOMIUM, has been developed by IMEC. This methodology will be used on a channel demodulator and decoder IC for Digital Audio Broadcast (DAB).
The main results of this project will be:
Philips (NL), Imec (b)
Contact Point Duration
Ir. Paul Lippens, 36 months from 01.11.97
Philips research laboratories
Prof. Holstlaan 4 (WAY 41), 5656 AA Eindhoven, (The Netherlands)
Tel: +31 40 27 44346
Fax: +31 40 27 44657
E-mail: lippens@natlab.research.philips.com
EP
25519 DESCALE
Summary
The market of smart cards is booming and the European semiconductor industry has a firm lead in the development and production of so-called smart card controllers. From a technology point of view, there are two important trends. Primarily, more and more functionality is added on-chip, requiring more computational power. Both the associated extra energy consumption and the extra heat removal (plastic is a poor heat conductor) are major challenges. Secondly, a large growth is expected in the market for contact-less cards, respectively dual-interface cards. Those cards collect energy from the electro-magnetic field applied to it from some distance. Here it is also critical to lower the peak current consumption.
DESCALE, a Design Experiment on a Smart Card Application for Low Energy, proposes the application of the highly innovative handshake technology to address both issues, aiming at some 5 times less power and some 10 times smaller peak currents compared to synchronously operated solutions. The required technologies are all represented in the consortium, so are the means to exploit the results. DESCALE can contribute to strengthen the European leadership in smart cards.
Participants
Philips Semiconductors (D), Philips Research (NL), Mikron (A), Mikroelektronik Anwendungszentrum Hamburg (D)
Contact Point Duration
Dr. Volker Timm 24 months from 1 November 1997
Philips Semiconductors Hamburg
(Germany)
Tel: +49-40-5613-2961
Fax: +49-40-5613-3313
E-mail: Volker.Timm@hamburg.sc.philips.com
EP
25599 SB-USB
Summary
The so-called Universal Serial Bus (USB) is a fast, bi-directional isochronous, low-cost, dynamically attachable serial interface for connecting a wide range of peripherals like telephone/fax/modem, answering machines, scanners, keyboards and mice to PCs. This new standard developed by Compaq, DEC, IBM, Intel, Microsoft, NEC and Northern Telecom is rapidly gaining acceptance across the entire PC industry.
All existing USB interface devices are implemented in 3 layers: the electrical interface handled by dedicated analogue hardware, the low-level protocol layers implemented in dedicated digital circuits, and the high-level protocol layers implemented in software. An implementation of all protocol layers in software would be valuable in terms of cost, flexibility, and versatility. In existing USB devices, however, the low-level protocol layers are implemented in hardware, since most available 8-bit microprocessor cores consume more power than available or provide only a fraction of the required processing speed.
In the meantime it was shown that CSEM?s CoolRISC microprocessor cores provide already 2/3 of the required processing speed (25 MIPS in 0.5u CMOS technology, while 36MIPS are needed) within the defined power constraints.
To reach the USB specifications, critical groups of USB instructions will be implemented in dedicated circuits and integrated as peripherals to the CoolRISC microprocessor core, such that they can be executed in a single microprocessor instruction.
Objectives
Xemics (CH), Logitech (CH)
Contact Point Duration
Vincent Rikkink, 18 months from 01.01.98
XEMICS SA
Rue de la Maladière 71,
CH-2007 Neuchâtel (Switzerland)
Tel: +41 32 720 54 27
Fax: +41 32 720 54 27
E-mail: vincent.rikkink@xemics.ch
EP
25615 SALOMON
Summary
The goal of SALOMON is the development of a design flow that allows a system-level exploration of mixed analog-digital telecommunication ASICs. Such exploration will allow high-level architectural trade-offs between an analog and a digital implementation of a given functional block in order to obtain the lowest overall power consumption. The design flow will allow system designers to simulate architectures by making use of high-level models of the circuits. Together with the high-level simulations, the overall power consumption will be monitored. To this purpose, high-level power estimators will be developed in this project for the different analog and digital blocks that are used in the examples.
Today analog-digital partitioning is typically performed in a heuristic manner by an experienced system designer and it is often strongly based on previous designs precluding the investigation of novel architectures that may consume less power. In order to make such system-level architectural explorations feasible without designing every sub-block down to the transistor level, the system designer must be able to simulate the entire system architecture at a behavioural level in order to verify the functionality and the performance. Existing simulation tools are not satisfactory to this end. In this project a new high-level design flow for mixed-signal telecom ASICs will be developed based upon the combination of system-level behavioural performance simulation and power estimators.
This general design flow could be implemented by means of a number of different software tools for simulation. In this project, one particular prototype implementation will be realised in order to illustrate the feasibility of the general design flow.
The main results of SALOMON will be
Participants
IMEC (B), K.U.LEUVEN (B), ALCATEL-MIETEC (B)
Contact Point Duration
Dr. Piet Wambacq, 36 months from 01.10.97
IMEC
Kapeldreef 75, B-3001 Heverlee
Tel: +32 2 16 281 223
Fax: +32 2 16 281 515
EP
25702 I-MODE
Summary
The main objective of I-MODE is to raise the level of integration in a DECT/DCS1800 transceiver, by implementing the necessary analog baseband low-pass filters and data converters in CMOS technology using low power techniques. The proposed work is closely related to and complements the OCMP Esprit Project (24123) and the ASPIS Esprit Project (20287). OCMP undertakes the development of a direct conversion transceiver for DECT/DCS1800 modes in a bipolar technology, whereas ASPIS undertakes the development of the baseband processing (DSP) function in a CMOS process for DECT/GSM/DCS1800 modes, operating from a 3V supply voltage.
In the I-MODE project, the required filters and data converters (not covered in the OCMP or ASPIS Projects) will be implemented, using low-power-effective techniques, such as current-mode, in a CMOS technology. The overall gain in reduced complexity, area and power consumption will be direct for the end product. As a matter of fact, the proposed action is an essential step towards a true one-chip system. Moreover, the use of low-power design methods can contribute to further lowering the power consumption profile for the end product. The project will facilitate the complete eventual integration of the analog/digital interface with the RF frontend (from OCMP) on a single BiCMOS chip or with the DSP (from ASPIS) to ultimately put all the baseband processing on a single digital CMOS chip.
With the successful completion of this project, the transfer of low power design techniques to practical use will be sufficiently addressed, and at the same time will enable a multi-mode portable phone to be offered to the market, using highly integrated low power components. In addition, INTRACOM's involvement in this low power design project will enable the company to improve its designs regarding analog and mixed analog-digital circuits, which can also be used in other designs concerning portable mobile phones. ICCS-NTUA will augment its low-power design expertise and adapt recently adopted design techniques - such as current-mode filters - towards the development of a real product.
Participants
INTRACOM (GR); INSTITUTE OF COMMUNICATIONS AND COMPUTER SYSTEMS-NATIONAL TECHNICAL UNIVERSITY OF ATHENS (GR)
Contact Point Duration
Mr. Dimitris Dervenis 18 months from 01.12.97
INTRACOM S.A.
19,5 km Markopoulou Ave
19002 Peania, GREECE
Tel: +30 1 6860456
Fax: +30 1 6860312
Homepage:www.intranet.gr/i-mode
EP
25710 CRAFT
Summary
The main objectives of the project are to develop low power and low voltage key RF blocks for highly integrated personal communication terminals and to derive a design methodology for such RF blocks based on the used CMOS technology. This Design Experiment is aimed on advanced architecture and circuit design to allow single chip integration of the base-band and RF section in CMOS technology for 2nd and 3rd Generation Mobile and Wireless Systems using the 900MHz and 2GHz band. The main areas of application for the developed circuits are for example the UMTS (W-CDMA, TD-CDMA), GSM, DECT and FLEX paging standards.
By designing, building and testing functional silicon prototypes, enhanced technologies for manufacture and assembly are to be developed in the field of advanced low power CMOS circuits. The prototypes are developed in three steps, component level, block level and system level, and are designed to serve as electronic building blocks in real products in wireless and mobile communications applications. Furthermore, the technology is considered to be suitable for the design of subsystems in the market segments of consumer products, automotive and other industrial applications.
Objectives
CSEM (CH), SGS-Thomson (F), CNET (F), Univerity Pavia (IT), EPFL (CH)
Contact Point Duration
Dr. Heiko Erben, 24 months from 01.01.98
Centre Suisse d?Electronique et de Microtechnique SA
Advanced Systems Engineering
Tel: +41 -32 / 7205 695
Fax: +41 -32 / 7205 720
EP
25716 PCBIT
Summary
OCTAL has developed and is presently commercialising a PCBIT board which plugs into the PC's ISA bus and allows an ISDN interface. The current PCBIT board uses off-the-shelf components based on the Siemens chipset. The objective of this project is to redesign this board in a PC-Card format with a PCMCIA interface so that the portable PC market can be targeted.
Essential for the success of a product in the portable market is its low power consumption. We propose to design an ASIC to integrate much of the functionality of the off-the-shelf components. We expect to achieve significant power savings by this process alone. Moreover, we plan to explore some power management techniques to further reduce power consumption.
Objectives
INESC (P), Octal (P)
Contact Point Duration
Prof. José C. Monteiro, 18 months from 01.11.97
IST / INESC
Rua Alves Redol, 9 - Sala 134 (Portugal)
Tel: +351 1 310 0283
Fax: +351 1 314 5843
EP 28593 COSAFE
Low Power Hardware-Software Co-Design for Safety-Critical Applications
Summary
The objective of the proposed experiment is twofold: first to develop a low-power co-design methodology for safety critical applications and a supporting design environment and second to develop, using the proposed methodology and design environment, a low power Application Specific Instruction set Processor (ASIP) that realizes the control unit of a portable infusion pump system, used in regulated continuous infusion of medicines in patient. The ASIP will lead to improved features demanded by the market and at the same time it will reduce the overall power consumption of the infusion pump system (including the motor consumption).
The proposed methodology aims mainly at a) the analysis of safety standards requirements and the determination of the safety mechanisms that will be implemented, b) the development of strategies for implementation of safety mechanisms, c) the introduction of power optimization techniques for both hardware and software implementation of safety critical tasks and d) the development of strategies for power-efficient assignment of safety-critical mechanisms to hardware or software components of heterogeneous architectures.
The COSAFE co-design methodology will be exploited in the development of both the ASIP and the application software, aiming at the minimization of the overall system power consumption and therefore enhancing the features of next-generation infusion pumps.
Objectives
Micrel Ltd. (GR), University Patras (GR)
Contact Point Duration
Alexandre TSOUKALIS, 29 months from 01.09.98
Micrel Ltd.
Ithakis 4
15344 PALLINI (Greece)
Tel. +30-1-6032.334
Fax +30-1-6032.335
E-mail: micrel@ath.forthnet.gr
EP 28564 MELOPAS
Methodology for Low Power Asic design
Summary
The partners, Schlumberger, XEMICS and CSEM, will closely collaborate to select modelling languages, design flow and simulation tools to evaluate at the system simulation the power consumption of mixed mode ASICs.
MELOPAS will be validated through the design
of a new ASIC.
Measurements on PC Boards will be correlated
with system level analysis.
The different stages of MELOPAS and its efficiency will be disseminated.
CSEM's objective is to develop a hardware/software co-simulation tool.
Schlumberger 's objective is to quickly achieve a drastic reduction on the power consumption of electronic equipment.
Schlumberger (F), CSEM (CH), XEMICS (CH)
Contact Point Duration
Luc BENOIT, 24 months from 01.09.98
Schlumberger Industries
Rue Ampere 9
71031 MACON (France)
Tel. +33 (0)3 85 29 39 56
Fax +33 (0)3 85 29 38 73
E-mail: benoit@macon.rms.slb.com
EP 28832 LUCS
Low Power Ultrasound Chip Set.
Summary
The specification, development and prototyping of a low power digital frontend for medical diagnostic ultrasound equipment. The goal of the project is to develop a low power chip set allowing to build up digital frontends with the quality and functionality close to that of high-performance systems for a price required in low-cost products and a power dissipation allowing their use in battery-operated handheld ultrasound scanners.
This should be realized by implementing the ADCs, the beamformer and the control in ASICs. Key technologies for this development are on-chip ADCs and dedicated low power VLSI circuits. This will lead to a key component with several ADCs, a beamformer and the necessary control on one chip. This chip will be used in a handheld ultrasound scanner (single chip solution) as well as in high-performance systems (cascaded multi-chip solution).
The analog part (IMS) of the project endeavors to transfer a design methodology for high-speed low-power ADC banks, which can be rather easily customized: The goal is scalability as far as architecture, performance, and technology are concerned.
The design of the proposed
beamformer (EECS) chip follows a low power design methodology applied on
all levels of CMOS design top from the algorithmic system level down to
the physical realization level. The full-custom design is reduced dramatically
by the use of a datapath generator.
Objectives
Participants
Pie Medical Equipment B.V. Maastricht NL
Fraunhofer-Institute, Duisberg Ge.
EECS group RWTH Aachen
Contact Point Duration
Ing. Joop Geijsen 36 months from 1.9.1998
Pie Medical Equipment B.V. Maastricht NL
Philipsstraat 1, 6227 AJ Maastricht (Netherlands)