SOC 설계 방법론, FALL, 2008

VADA Lab.
School
of Information and Communication,  Sungkyunkwan University


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Lecturer: Prof. Jun-Dong Cho Email: jdcho@yurim.skku.ac.kr , Room 21203A, Office:031-290-7127

Office hours: after class, and by appointments. 

Grading:      Projects:          30%,   Final Exam:   60%

                     Presence:        10% (F-grade will be given if there is more

 than 5 absences)

Course description

This course covers the Embedded system design and implementation of System on chip with multiple processor cores such as  DSP's, GPP's, and FPGA's with particular focus on the architectues under constraints of speed, power, and area. Several case studies will be presented, along with their highly optimized dedicated designs, which exploit relationships between the algorithm and hardware architectures.  To enhance the SoC design capability, we explore the SoC Components and their interconnect structures. By understanding the embedded system's structures and architectures, we understand the operation of each components of embedded system.  We also study a reconfigurable signal-processing platform for Software Defined Radio (SDR).

과정은 다양한 프로세서 코어(DSP, GPP) IP(ASIC,FPGA) 내장한 시스템 임베디드 시스템 설계시 전력, 속도 면적 제약조건을 고려한 구현방법을 다룬다알고리즘 하드웨어 구조사이의 관계를 탐구하여 최적화된 구조를 찾는 것을 목적으로 한다. 또한, SoC 구성하는 구성요소 연결 구조를 탐구하고, 구성요소의 구조   동작과정을 공부하며  SoC응용 플랫폼으로  소프트웨어 디파인드 래디오구조 설계 방법에 대해서 알아본다.