Previous Projects

3D Auto-Convergence and its applications using Real-time Depth-map (with Samsung Electronics, 2010.03.01 ~ 2011.02.28)

  • This project aims to identify and develop an quality-enhanced 3D image processing, utilizing 3D depth information acquired by 3D camera of Mobile Devices. Throughout our research works, following techniques will be developed.
    • 1) Improvement of quality for real-time depth-map acquisition system to be applied for core ingredients of 3D camera system.
      • Rectification, real-time depth-map, Segmentation system realization using Stereo Camera : Algorithm and hardware design
      • Auto-convergence system utilizing real-time depth-map acquisition: Improvement of quality and Algorithm development aiming for HD 30 fps.
      • 3D Asymmetric Stereo Registration, Depth focus: VGA, 30fps
    • 2) Innovative technology of real-time high speed and cycle-accurate low power RTL structure will be exploited and verified using FPGA.
      Publications
      • "A Real-time 3D Image Refinement Using Two-line Buffers", the 13th International Conference on Advanced Communication Technology, Feb. 2011
      • "Real Time Rectification Using Differentially Encoded Lookup Table", The Fifth International Conference on Ubiquitous Information Management and Communication, Feb. 2011.


Multi-purpose 3D Multimedia SoC for Robot Applications

  • This project aims to develop a quality-enhanced 3D image processing, including 3D camera sensing and robot's cognitive recognition/modeling. Throughout our research works, the following techniques will be developed.
    • Improvement of quality for real-time 3D camera acquisition and recognition system and its real-time realization.
    • Real-time Realization of 3D graphic acceleration Engine
    • Development of Multi-Master System Bus for real-time System on Chip
    • Innovative high speed and cycle-accurate low power RTL structure will be exploited and verified using FPGA.

Low Power Design Techniques

  • Low Power Bus Binding Exploiting Optimal Substructure: The earlier stage we perform low power design, the higher dynamic power reduction we achieve. In this work, we focus on reducing switching activity in high-level synthesis, especially, in the problem of functional module binding, bus binding or register binding. We propose an effective low power bus binding algorithm based on table decomposition method so as to reduce switching activity. The proposed algorithm is based on the decomposition of the original problem into sub-problems by exploiting the optimal substructure, and as a result, it finds optimal or close-to-optimal binding solution with faster computing time. Experimental result shows that the proposed method obtains a 2.3~22.2% better solution than one of conventional heuristic method, with 8.0~479.2 times faster than optimal ones (at threshold value of 1.0E+9).
  • FPGA-based Instruction-Level Low Power Simulator: This is the power consumption estimation tool used for the embedded system. Each instruction in Core-A processor is first measured using FPGA X-power simulator. Using the instruction power consumption look-up table, instruction level power consumption of C-code is measured. With this scheme, we can identify lower power coding style conveniently.

이동로봇을 위한 3차원 적외선 카메라 영상처리 프로세서 (과학기술부 2004.05.~2006.04)

H.264/AVC 인코더/디코더 IP 개발 (한국전자부품연구원, 2007.09~2009.08)

디지털 방송처리 멀티미디어 개발 (삼성전기 2007.10~2008.05)

3D Image Processor Prototype Board (과학기술부, 2007.03 ~ 2008. 02.)

Multiprocessor SoC Platform for DVB-T Baseband Receiver (ETRI, 2005.03 ~ 2006. 02.)

IEEE 802.15.4 ZigBee Demodulator의 FPGA Test보드 및 ASIC 구현 (Samsung Electro-Mechanics, , 2005.03 ~ 2006. 02.)

ARM-based Multiprocessor SoC Platform Verification Methodology (IT-SoC Center , 2006.03 ~ 2007. 02.)

인간기능 생활지원 지능로봇을 위한 삼차원 물체 추적 data 처리 가속 엔진 SoC 개발 (MOST, 2003. 10 ~ 2006. 03)

High-Flexible Signal Processing Chip Design of OFDM Transceiver for DVB-T (Samsung Electronics, 2002.03.01 ~ 2003.02.28)

치과용 동영상 디지털 x-선 디텍터 시스템 개발 (SMBA, 2007. 8.~ 2009. 7)

High Speed Encryption System SoC (MOCIE, 2003. 8.~ 2005. 7)

Development of Data Drive IC for Field Emission Display (Samsung Advanced Institute of Technology, 2003.05.~ 2004. 03)

POD Copy Protection of CableCard Conditional Access System designed using System C (Samsung Electronics, 2003.03~ 2004. 02.)

Sensor-network-based Mobile Homecare Monitoring System (Wireless Internet Research Institute, 2003.03 ~ 2004. 02.)

Cable Modem Equalizer for xDSL


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jdcho@skku.edu

(c) VADA Lab.