This course studies computer-aided design algorithms with complex VLSI
We discuss especially on up-to-date deep submicron layout synthesis issues
on large-scaled VLSI circuit designs.
The physical layout problems to be discussed in this course are: partitioning
and floorplanning/placement, global and detailed routing, timing-driven layout,
power and ground routing, clock synthesis,
lower power synthesis and MCM layout.
This course will also cover the state-of-the-art lower power design
techniques and hardware/software codesign techniques.