VLSI Design Optimization, 1997 Fall


  • This course studies computer-aided design algorithms with complex VLSI circuits. We discuss especially on up-to-date deep submicron layout synthesis issues on large-scaled VLSI circuit designs. The physical layout problems to be discussed in this course are: partitioning and floorplanning/placement, global and detailed routing, timing-driven layout, power and ground routing, clock synthesis, lower power synthesis and MCM layout. This course will also cover the state-of-the-art lower power design techniques and hardware/software codesign techniques.
  • Instructor : Prof. Jun-Dong Cho (jdcho@yurim.skku.ac.kr)(office: 0331-290-7127)

    Lecture Room: Seminar Room

    Lecture Hour: Thursday 19:00 - 21:50

    Evaluation

    Homework (20%), Project (30%), Attending (10%), Seminar (10%), Final Exam (30%)


    Agenda



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