PROF. JUN-DONG CHO'S
DISTINCTIVE ACHIEVEMENT
Professor Jun-Dong Cho has a strong background on VLSI
Design optimization and he is well-known as one of pioneers in the area of ¡°high
speed physical design of Multi-chip Modules and packages.¡± and
also high speed and low power communication intellectual property VLSI
design. Of particular interest of his research area is to cover both
design optimization and synthesis in terms of performance,
area and low power consumption. Because of the increasing importance
of interconnect and power consumption in modern
VLSI systems, he has been expanding his research areas to cover recent
demands on system on chip applications.
For 23 years, he has
contributed to the advancement of computer-aided VLSI and System-on-chip
design targeting small area, lower power and higher flexibility. He has
had a lasting impact on VLSI CAD society by
publishing awarded papers and performing about 40 projects supported by
governments and industries.
Research Awards:
1.2005. 11: Vice- Minister Prize, Best BK21 project
(with Prof. H.S. Choo,
H.J.Choi, B.W.Jeon), Korean Science
Engineering Foundation
2. 2005. 10: Best Project Demonstration, IT-SOC 2005
& Next Generation PC Industrial Exhibitions
3. 2005. 3: Inclusion in 2006 (23rd) Edition, Marquis'
Who's Who in the World
4. 2004 Best Research 30's (With H.J.Choi
and H.S.Choo), "Embedded OS-based Wireless Multimedia Access Module in Personal
Networks", Korean Science Engineering Foundation
5. 2001. 5: The first Patent Application Invention
Achievement Award, IBM
6. 2001. 4: Best Research Professor Award in School of
Electrical and Computer Engineering,
Patents:
1. "Lower Power Bus Encoding", Jin Woo Kim,
Jun Dong Cho, Young-Hoon Chang,
10-0455274 with Samsung Electronics, 2004.10.22
2. Viterbi Decoder ADS
Module,
3. Low Power Viterbi
Decoder,
4.Timing-Driven Multi-Level Partitioning and Placement using
Geometry-aware Timing Budgets, Jun-Dong Cho and David Kung.
5. Adaptive Digital Filter, Jun-Dong Cho, H.S. You, et
al, 2002-0037397, 2002.05.21
BEST PAPER AWARDS:
1. 2002. 4: Samsung Human Tech Contest Prize with
2. 2000. 5: Best Paper Award with Bo-Sing Kim,
Jun-Dong Cho, Young Hoon Chang, "Fast and Low
Power Viterbi Search Engine using Inverse Hidden
Markov Model" , pp.169-173, IEEK Workshop on CAD and VLSI Design, May
2000.
3. 1998. 11: Best Paper Award with San Kim, Kwang-Youl Lee, and Jun-Dong Cho, "Minimum-Crosstalk
Top-Down Global Routing", IEEK Conference on VLSI
and CAD, pp. 277-278, 1998
4. 1994.5: Best paper Award with M. S. Chang,
Crosstalk-Minimum Track
Reassignment, Samsung Electronics
Semiconductor Technical Report vol.9 no. 1.
5. 1993.6: Best Paper Award with Majid Sarrafzadeh, Buffer Distribution
Algorithm for High-Speed Clock Routing', IEEE/ACM Design Automation
Conference, pages 537-543.
His research area of the most distinct contributions:
1)VLSI Layout Design Automation, 2) High Speed
and Low Power System on Chip Design.
Prof. Cho's distinct
contribution to VLSI layout design automation (projects performed):
1)Multichip-Module pin distribution with concurrent
Maze-router-based Global routing
2)Clock network design with buffer distribution
3)Circuit partitioning with graph matching and its applications and
4)Multilayer Routing and Placement Algorithm for MCMs
and packages 5)Wiring Space Estimation 6) Reticle
Frame Key Layout Placer for IC Reticles, 7) Lower
Power Physical Design considering logic designs in Deep-Submicron, 8) Low-Power
Channel Router for Deep-submicron VLSI, 9) Crosstalk Noise and Defect Area
Minimization, 10) Memory Peripheral Shaped-based Router (Multilayer Gridless Area Router), 11) Timing-Driven Multi-Level
Partitioning and Placement
Prof. Cho's distinct
contribution to High speed and low power System on Chip design(projects
performed):
1) SoC-based Platform for
Development of FED Image Processing Circuit, 2) ARM-based Multiprocessor on
Chip Partitioning for H.264 Decoder, 3)
Heterogeneous QoS on Chip
Multi-processor Platform for Highly Flexible Software Defined Radio Systems, 4)
Low Power ASIC Design for IEEE 802.15.4 Zigbee Modem,
5) High Speed Viterbi Decoder
ASIC design for UWB, 6) HW and SW Codesign for DVB-T
Receiver, 7) POD (Copy Protection; Conditional Access System) Designs using
System C, 8) HW/SW Codesign on CDMA system for ASIC
Designs, 9) Low-Power High Level Synthesis by Reducing Switching Activities,
10) Mobile Homecare Monitoring System, 11) High-Flexible Signal Processing Chip
Design of OFDM Transceiver for DVB-T, 12) Low Power and High Performance
Reconfigurable Equalizer for Cable MODEM, 13) Fast and Low Power Search Engine
for Speech Recognition, 14) Lower Power CDMA Decoder for Convolutional
Encoder, 15) Low Power Viterbi Scorer for HMM-based
Isolated Word Recognition, 16) Low Power Motion Estimation by Maximizing Memory
Data Reuse, etc.
From Mar. 2005 to Feb. 2006, he has consulted Multiprocessor
System on Chip Design Automation,at
the SoC Center, Samsung Advanced Institute of
As shown in the above, Prof. Cho's
research attributes is to continuously expand his VLSI computer-aided design
research scope to the emerging System on chip applications.
OTHER TECHNICAL ACCOMPLISHMENT
1. Jun-Dong Cho and M. Sarrafzadeh, "A Buffer
Distribution Algorithm for High-Performance Clock Net optimization
", IEEE Trans. on Very Large Scale Integration Systems, Vol. 3, No.
1, pp. 84- 98, March 1995. (Preliminary
version received a Best paper award at 1993 IEEE&ACM
Design Automation Conference)
Professor Cho is a pioneer for the development of
Optimization of Clock
Distribution Networks?in particular to the application to Very Large
Scaled
Integrated Circuit. The solution provided a practical
guideline to provide a
good tradeoff between skew and wire-length, based on a
combination of
hierarchical bottom-up geometric matching and minimum rectilinear
Steiner
tree. Professor Cho developed the theory of the total
weight of a worst-case
rectilinear hierarchical matching tree in the unit square is at
most twice the
total weight of a worst case minimum rectilinear Steiner Tree.
Professor Cho also invented a fundamental
algorithm on how to redistribute the buffers evenly over the routing plane
avoiding congestion considering wire length, skew and phase-delay. The problem
is formulated as the degree and length minimum spanning tree problems and a
polynomial time algorithm was invented with some upper-bounds on both metrics.
The techniques described in this publication has
directly led to development of clock tree optimization technique used for
Samsung Electronics and companies in
2. J.D. Cho and M. Sarrafzadeh. ``Pin Redistribution Algorithm for
Multi-Chip
Modules'' Mathematical Programming B: 63, pages
297--330, Dec. 1994. Its
Extension: J.D. Cho, "An Optimum Pin
Redistribution for Multi-Chip Modules", Proceedings of Multi-Chip Module
Conference,
Professor Cho invented a Pin Redistribution Technique.
The problem is to redistribute the pins uniformly over the MCM substrate using
a number of pin redistribution layers. Professor Cho also invented a new
Concurrent Maze Router.The techniques in this
publication have directly led to the recent high-density packaging techniques,
for example, Redistributed Chip Packaging by Freescale
semiconductor.
Professor Cho's works were
published as a book High-Performance Physical Design for MCM and
Packages,co-authored with Paul Franzon,
World Scientific Co., Oct. 1996
3. (U.S. Patent) US 6480991B1, Jun-Dong Cho, David
Kung (IBM), Timing-Driven Multi-Level Partitioning and Placement using
Geometry-aware Timing Budgets, Nov. 12, 2002
This is the original invention of a timing-budget
management technique which satisfies triangle inequality, a timing-driven
quadric-section placement strategy based on flexible timing window
configurations to minimize the wire-length and congestion. Professor Cho
innovatively developed theoretical analysis and provided the pioneer principle
between timing budgets and triangle inequality property during 4-way
partitioning.
1) VLSI Layout Design Automation.
1. Jun Dong Cho, Kuo-Feng Liao, Salil Raje,
and Majid Sarrafzadeh, "M2R:
Multilayer Routing Algorithm for High-Performance MCMs", IEEE Trans. on Circuit
and Systems-I: Fundamental Theory and Applications, Vol. 41, No. 4, pp.
253-265, April 1994.
2. Jun-Dong Cho, S. Raje and
M. Sarrafzadeh, "Fast Approximation Algorithms on maxcut,
k-Coloring and k-Color ordering for VLSI Applications", IEEE Trans. on
Computers , Vol. 47, No. 11, pp. 1253-1266, Nov. 1998. Preliminary version: New
Approximation Results on Graph Matching and related Problems, Y Kajitani,
JD Cho, M Sarrafzadeh - Proceedings of the 20th
International Workshop on Graph '94, Herrsching,
Germany (Lecture Notes in Computer Science, volume 903, pages 343-358. Spring-Verlag), 1994.
3. J.D.Cho and M.
Sarrafzadeh, "Four-bend Top-Down Global Routing", IEEE Trans. on CAD
of Integrated Circuits, Vol. 17, No. 9, pp. 793-802, September 1998.
4. J.D.Cho, "Wiring Space
and Length Estimation in Two-Dimensional Arrays", IEEE Trans. on CAD of
Integrated Circuits, Vol. 19, No. 5, pp. 612-615, May 2000.
5. Wiley Encyclopedia of Electrical and Electronics
John Wiley and Sons, Inc. Co-authored with M.
Sarrafzadeh, April, 1999. Also, Professor Cho is the author of the invited
chapter "Steiner Tree Problems in VLSI Layout Designs" in the book
"Steiner Trees in Industries" Kluwer
Academic Publishers. May 2001, editors: Ding-Zhu Du
and Xiuzhen Cheng. The chapter facilitates
engineering research and education for this emerging technology and opens
several research topics to researchers and engineers. The solutions can also be
used in other societies such as Transportation and Communication Networks.
2) Communication and Multimedia System on Chip designs
for low power consumption.
1. Bo-Sung Kim and Jun-Dong Cho, "Maximizing
Memory Data Reuse for Low Power Motion Estimation,VLSI
Design, Vol 14, No 2, pp. 295-305, 2002
2. B.K. Park, K.S. Cho and J.D. Cho, Low Power VLSI
Architecture of Viterbi Scorer for HMM-based Isolated
Word Recognition,?IEEE International Symposium on
Quality Electronic Design, pp.235-239, Mar. 2002. (Its extension version
received 밪amsung Human Tech. Contest Prize,April 2002)
3. J.H. Ryu, S.C. Kim, J.D.
Cho, H.W. Park, Y.H. Chang , Lower Power Viterbi
Decoder Architecture with a New Clock-gating Trace-back Unit? International
Conf. on VLSI and CAD, 1999 (patent: 1) Viterbi
Decoder ADS Module, Hyunwoo Park, Je
Hyunk Ryu, Jun Dong Cho,
Young-Hoon Chang, No. 2001-0068415 with Samsung
Electronics, 2001.07.23 2) Low Power Viterbi Decoder,
Sun Hee Park, Young-Hoon Chang, Je-Hyuk
Ryu, Jun-Dong Cho No. 2001-0073699 with Samsung
Electronics, 2001.08.01
4. B.S.Kim and Jun-Dong Cho,
Fast and Low Power Viterbi Search Engine Using
Inverse Hidden Markov Model? IEICE Transactions on Fundamentals, Vol. E87-A,
no.3 pp.695-697, March, (Preliminary version received Best Paper Award at IEEK
Workshop on CAD and VLSI Design,
5. Professor Cho is the author of the invited book
"Lower Power Digital Core Design for Multimedia and
Telecommunications (in English)", IC Design and
Also, he developed three e-learning materials for
engineers in industry such as 1) Low Power Design(16 hours) @ http://www.baeoom.com,
Korea 1July 1999; 2) Software Defined Radio10 hours) @ RF Engineering
Research Center, Information and Communication University, Korea Sep. 2004; 3)
Fundamental to Cellular Communication Development Platform, Samsung
Electronics Co. Dec. 2006.The lecture contents facilitated research and
education. These books bridge the gap between two engineering experts: VLSI
Design and System on Chip Signal Processing.
AWARDS, OFFICES HELD, COMITTEE MEMBERSHIPS
Awards:
1. June 1996: IEEE Senior Member
2. June 1993: Best Paper Award with Majid Sarrafzadeh,
Buffer Distribution Algorithm for High-Speed
Clock Routing'' in the 30th IEEE/ACM Design Automation Conference, pages
537-543,
3. Nov. 2005: Vice- Minister Prize, Best BK-21 project
(with Prof. H.S. Choo, H.J.Choi,
B.W.Jeon), Highly Flexible Mobile Computing, Korean
Organization of Science and Engineering Foundation
4. Oct. 2005: Best Project, Hardware Software
Co-design Methodology, IT-SoC, Ministry of
Information and Communication,
5. April 2002: Samsung Human Tech. Prize (with B. K.
Park), "Low Power VLSI Architecture of Viterbi
Scorer for HMM-based Isolated Word Recognition.?6. May 2001: The First Patent
Application Invention Achievement Award , IBM
7. April 2001:Best Research
Professor, School of Electrical and Computer Engineering,
8. Dec. 2000: Meritorious Award, CAD and VLSI society
of the
9. May 1994: Best paper Award (with M. S. Chang),
``Crosstalk-Minimum Track Reassignment'', Samsung Electronics.
10. Aug. 1993: Meritorious Award, Samsung
Semiconductor &Telecommunication.
Committee Memberships:
1. Dec. 2006 ~ Current: In Organizing Committee, IEEE
Asian Pacific-Design Automation Conference?8,
2. Feb. 2004 ~ Current: In Organizing Committee, Int?SoC Design Conference, sponsored
by IEEE EDS/SSCS,
3. Aug. 2003: In Program Committee, IEEE Int' Symposium on Low Power
Electronic Design,
4. Nov. 2003: In Program Committee and Best Paper
Selection Committee, International Conference on
Computer Aided Design, San Jose
5. Feb. 2003: In Program Committee, IEEE Asian Pacific
Design Automation Conference, Kita-Kyushu
6. Sep. 2005: In Program Committee, Int¡¯ Symposium on Quality of Electronic Design, San Jose
7. Jan. 2000: In Program Committee, IEEE Asian-Pacific
Design Automation Conference, Jan 26-28.
8. Apr. 2000: In Program Committee, Symposium on
System Level Interconnection Prediction,
9. Nov. 1999: In Programming Committee, IEEE Int¡¯ Conference on VLSI and CAD,
10. Aug. 1999: Tutorial Chair of IEEE Asia-Pacific
Conference on ASIC,
11. Jan.1998 ~ Jan. 2000: Educational Activity Chair,
IEEE EDS/SSC Seoul chapter
12. Apr. 1997: Session Chair of IEEE Int¡¯ Symposium on Physical Design, Nappa
13. Feb. 1997: In Programming Committee and
14. Jan 1997: In Programming Committee, Int¡¯ Conference on VLSI Design,
Bangalore
16. 1999 ~2001: Guest Editor of VLSI DESIGN: Special
Issues: 1) Low Power
Architecture Design 2) Low Power CAD 3) Physical
Design Automation in Deep Submicron 4) High
Performance Interconnection Designs
17. Feb. 1999 ~ Feb. 2002: Associate Editor of Journal
of Electrical Engineering and Information
Science
18. May 1999: Organizing Committee Chair, CAD and VLSI
Design Workshop,
19. Feb. 1997 ~ Feb. 1999: Associate Editor of Journal
of Institute of Electronic Engineer of
20. Aug. 1994 ~ Jan. 1996: Guest Editor of the
International Journal of High-Speed Electronics
Design Automation of Multi-Chip Modules and Packages.
OTHER NOTABLES
Especially, Preofessor
Jun-Dong Cho was invited by Dagstuhl
Seminar Theory and Practice of Physical Design of VLSI Systems, hosted by T. Lengauer, R. Moring and B. Preas, Schloss Dagstuhl,
He is well-known as one of pioneers in the area of
High speed physical design of Multi-chip Modules and packages.and
also high speed and low power communication intellectual
property VLSI design.
Of particular interest of his research area is to
cover both design optimization and synthesis in terms of performance,
area and low power consumption. Because of the increasing
importance of interconnect and power consumption in
modern VLSI systems and the fact that these fields of
research have gained a certain degree of maturity in recent years, he has
been expanding his research areas to cover recent demands on system on
chip applications,
Prof. Cho was acknowledged in Prof, C.K.Cheng's book, Interconnect analysis and Synthesis,published by John Wiley
& Sons, Inc., 2000. . Several research groups have made significant
contributions in the field and the reader is encouraged to investigate their
works. Key contributors to progress in interconnect oriented design automation
include Jason Cong and Andrew Kahng (UCLA), Gabriel Robins (U. Virginia), Majid
Sarrafzadeh (NWU),
Sachin Sapatnekar (U. Minnesota), Massoud Pedram (USC), Eby Friedman (U. Rochester), Kurt Antreich
(Technical Univ. Munich), Pak Chan (UCSC), Jun-Dong Cho (Sungkyunkwan
Univ.), Cheng-Kok Koh
(Purdue), Xianlong
Hong (Tsinghua Univ), Steve Kang (UIUC), C.L. Liu (Tsing
Hua Univ.), Tatsuo Ohtsuki
(Waseda), Takayasu Sakurai
(Tokyo Univ.), Jacob White (MIT), CK Wong (Chinese Univ. Hong Kong), and Dian
Zhou (UNCC).
Prof. Jun Dong Cho was served for Educational Activity
Chair?in IEEE ED/SSC
Seoul Chapter 1998-2000. He was very actively
serving the educational activities such as workshop organization by
inviting IEEE Distinguished Lecturers from overseas
With his effort, the IEEE ED/SSC Seoul Chapter received the IEEE Solid State
Circuit Society 2001
Outstanding Chapter Award by
organizing committee of the First Asia Pacific
Conference on ASIC (organized by the IEEE ED/SSC Seoul Chapter), 2003
He is an IEEE Senior member since 1996 and contributed
to Korean IEEE Society in many ways.
Some of them are as follows: In 1999, he served as an
organization chair of the fifth CAD and VLSI Design Workshop, where he
introduced English-presentation session and English-presentation Paper Prize.
Since then, he became one of the contributors for
globalizing local Korean Conference such as Conference on VLSI and CAD and
System on Chip Conference to make them IEEE-sponsored international conferences.
The other his contribution is his Korean CAD and VLSI
E-mail Newsletter (http://vada.skku.ac.kr/jdcho/kvn.html) that provides
information on international conferences and other on-line material.
This on-line E-mail news letter is subscribed by 2000 Korean CAD and VLSI people and also linked in Microelectronic
Systems News operated by Prof. Donald W. Bouldin,
Recently,
world-first graduate program called "celluar
phone department" such that all graduate students are
guaranteed to work
for Samsung Electronics after graduation. Now he is
serving for steering committee and also SoC team
leader of the Department.